Jiahe Shi

I am a master student advised by Prof. Jun Tao at Fudan University, where I received my B.S. degree. I am very lucky to work with Prof. Zhiru Zhang on ML for EDA at Cornell University, Prof. Yiyu Shi on Federated Contrastive Learning at the University of Notre Dame, and Prof. Peng Li on statsitical model for EDA at University of California, Santa Barbara. (chronically)

My research interest is at the intersection of machine learning and system/hardware design.

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News
  • [Oct. 2023] Win National Scholarship at Fudan University again!🎉
  • [Sept. 2023] One paper got accepted by TODAES!🎉
  • [July 2023] Working with Prof. Zhiru Zhang at Cornell University as a summer intern!👩‍💻
  • [April 2023] One first author paper got accepted by TCAD!🎉
  • [Jan. 2023] One paper got accepted by JSSC!🎉
  • [Sep. 2022] Win KLA Scholarship for Excellent Graduate Students at Fudan University (top 1%)!🎉
  • [June 2022] Working with Prof. Yiyu Shi at the University of Notre Dame as a summer intern!👩‍💻
  • [Jan. 2022] One paper got accepted by ISCAS 2022!🎉
  • [Sept. 2021] Working with Prof. Jun Tao in Fudan University as a master student!👩‍💻
  • [June 2021] Graduate from Fudan University as Excellent Graduate Student in Shanghai!👩‍🎓
  • [Oct. 2020] One first author paper presented at ISCAS 2020 !🎉
  • [Sept. 2020] Win National Scholarship for Excellent Undergraduate Students at Fudan University (top 1%) !🎉
Publications
Self-supervised On-device Federated Learning from Unlabeled Streams

Jiahe Shi, Yawen Wu, Dewen Zeng, Jun Tao, Jingtong Hu, Yiyu Shi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023
[paper]

The first work that enables learning visual representations from unlabeled streaming data on resource-restricted distributed devices.

Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9–14.3-GHz 85-fs-rms Jitter PLL

Yizhuo Wang, Jiahe Shi, Hao Xu, Shujiang Ji, Yiyun Mao, Tenghao Zou, Jun Tao, Hao Min, Na Yan
IEEE Journal of Solid-State Circuits (JSSC), 2023
[paper] [bibtex]

Developed an algorithm to automatically optimize the capacitor array in a wideband VCO.

Multi-Corner Parametric Yield Estimation via Bayesian Inference on Bernoulli Distribution with Conjugate Prior

Jiahe Shi, Zhengqi Gao, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng
IEEE International Symposium on Circuits and Systems (ISCAS), 2020
[paper] [bibtex]

A novel Bayesian Inference method based on Bernoulli distribution with conjugate prior to efficiently estimate parametric yields over multiple PVT corners.

Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Networks: Enhancing Circuit Reliability under Environmental Variation

Nanlin Guo, Fulin Peng, Jiahe Shi, Fan Yang, Jun Tao, and Xuan Zeng
ACM Transactions on Design Automation Electronic System (TODAES), 2023
[paper] [bibtex]

An efficient Bayesian optimization method based on Bayesian neural network for yield optimization in multiple environmental corners.

NIMBLE: A Neuromorphic Learning Scheme and Memristor Based Computing-in-Memory Engine for EMG Based Hand Gesture Recognition

Fengshi Tian, Jingwen Jiang, Jinhao Liang, Zhiyuan Zhang, Jiahe Shi, Chaoming Fang, Hui Wu, Xiaoyong Xue, Xiaoyang Zeng
IEEE International Symposium on Circuits and Systems (ISCAS), 2022
[paper] [bibtex]

A new neuromorphic learning and computing approach for electromyogram (EMG) based hand gesture recognition tasks.

Projects
The Straggler

A vertically scrolling shooter video game implemented using C++ in attribution to the classical shooting game, Raiden.
  • The player can take control of an aircraft to defeat the enemy aircraft and save the Earth.
  • Single-player and co-op modes are developed and can be selected by the player.
  • The game consists of five stages with increasing difficulty, various projectiles, background music, and action audio effects.
  • Various functions are implemented, including pause, exit, customized setting, and help.

Facial Expression Recognition System Based on Zybo

A hardware-software co-design system for facial expression recognition via deep neural networks.
  • An ARM processor reads pre-saved images from DDR, then processes them through neural networks implemented in FPGA. The recoginition results are displayed on a screen via a VGA port.
  • We used Vivado HLS to design the IP cores of resize, convolution, and pooling.
  • We constructed a display data path using Vivado IPs.
  • We assigned some DNN computing to an ARM processor on the Zybo Z7 board due to limited computation resource.